* fixed issue with missing "net" definitions of power input and output pins
* finished layout
This commit is contained in:
parent
3ac30bdf92
commit
c3efc67faa
3 changed files with 25 additions and 16 deletions
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@ -28,6 +28,10 @@ T 51500 49600 5 10 1 1 0 0 1
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refdes=POWER_IN
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T 51500 48800 5 10 0 0 0 0 1
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footprint=HEADER2_1
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T 51500 48800 5 10 0 0 0 0 1
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net=VCC_HIGH:1
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T 51500 48800 5 10 0 0 0 0 1
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net=GND_LED:2
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}
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C 55500 48800 1 0 1 connector2-1.sym
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{
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@ -37,22 +41,18 @@ T 55500 49600 5 10 1 1 0 6 1
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refdes=POWER_OUT
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T 55500 48800 5 10 0 0 0 0 1
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footprint=HEADER2_1
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T 55500 48800 5 10 0 0 0 0 1
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net=VCC_HIGH:1
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T 55500 48800 5 10 0 0 0 0 1
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net=GND_LED:2
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}
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N 53200 49000 53800 49000 4
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{
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T 52800 48800 5 10 1 0 0 0 1
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netname=GND_LED
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}
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N 41500 47000 41500 48500 4
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{
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T 41500 47200 5 10 1 1 90 0 1
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netname=GND_uC
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}
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N 53200 49300 53800 49300 4
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{
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T 52800 49400 5 10 1 0 0 0 1
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netname=VCC_HIGH
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}
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C 53300 44700 1 0 0 connector6-2.sym
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{
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T 54000 47600 5 10 1 1 0 6 1
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@ -1,11 +1,11 @@
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unnamed_net3 D1-1 L1-2
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unnamed_net2 R1-2 Q1-2
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unnamed_net1 D2-1 L1-1 Q1-3
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GND_LED D1-2 D2-2
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GND_LED D1-2 D2-2 POWER_OUT-2 POWER_IN-2
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PWM_LED R1-1 CONF-3
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GND_uC COMM_BUS-5 COMM_BUS-6 COMM_BUS-4 CONF-15 CONF-13 CONF-11 CONF-9 CONF-7 CONF-5 MOVEMENT_SENSOR-3 uC-14
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uC_CONF_SERIAL COMM_BUS-3 uC-13
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VCC_HIGH R2-1 CONF-1 uC-12
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VCC_HIGH R2-1 POWER_OUT-1 POWER_IN-1 CONF-1 uC-12
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CURRENT_CONTROL_LOW R2-2 Q1-1 uC-11
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SENSOR_IN CONF-16 MOVEMENT_SENSOR-1 uC-10
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uC_CONF_D CONF-14 uC-8
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@ -1,5 +1,5 @@
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# release: pcb 20091103
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# date: Sat Dec 19 01:45:52 2009
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# date: Sat Dec 19 02:41:18 2009
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# user: lars (,,,)
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# host: erker
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@ -802,6 +802,8 @@ Via[170000 30000 5600 2000 0 2000 "" ""]
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Via[150000 30000 5600 2000 0 2000 "" ""]
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Via[180000 20000 5600 2000 0 2000 "" ""]
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Via[80000 0 5600 2000 0 2000 "" ""]
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Via[70000 20000 3600 2000 0 2000 "" ""]
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Via[110000 10000 3600 2000 0 2000 "" ""]
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Element["" "HEADER2_1" "POWER_IN" "unknown" 10000 40000 15000 -1000 0 100 ""]
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(
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@ -987,10 +989,10 @@ Element["" "SIP3" "MOVEMENT_SENSOR" "unknown" 170000 10000 4000 11000 2 100 ""]
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Layer(1 "component")
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(
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Line[200000 0 80000 0 1000 2000 "clearline"]
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Line[110000 10000 40000 10000 1000 2000 "clearline"]
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Line[60000 90000 60000 80000 1000 2000 "clearline"]
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Line[70000 98802 70547 99349 1000 2000 "clearline"]
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Line[39896 100000 40547 99349 1000 2000 "clearline"]
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Line[40000 10000 40000 40000 1000 2000 "clearline"]
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Line[50547 90349 59651 90349 1000 2000 "clearline"]
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Line[70000 40000 60000 40000 1000 2000 "clearline"]
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Line[170000 10000 170000 0 1000 2000 "clearline"]
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Line[140000 50000 120000 50000 1000 2000 "clearline"]
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@ -1018,10 +1020,10 @@ Layer(1 "component")
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Line[90000 60000 90000 30000 1000 2000 "clearline"]
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Line[190000 30000 190000 40000 1000 2000 "clearline"]
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Line[90000 30000 190000 30000 1000 2000 "clearline"]
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Line[70000 40000 70000 20000 1000 2000 "clearline,rubberend"]
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Line[60000 90000 60000 80000 1000 2000 "clearline"]
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Line[50547 90349 59651 90349 1000 2000 "clearline"]
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Line[59651 90349 60000 90000 1000 2000 "clearline"]
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Line[10000 40000 10000 50000 2500 2000 "clearline"]
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Line[10000 10000 10000 40000 1000 2000 "clearline,rubberend"]
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Line[10000 10000 110000 10000 1000 2000 "clearline"]
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)
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Layer(2 "solder")
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(
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@ -1061,6 +1063,9 @@ Layer(2 "solder")
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Line[51000 88896 50547 89349 1000 2000 "clearline"]
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Line[50547 90349 50547 68453 1000 2000 "clearline"]
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Line[50547 68453 50600 68400 1000 2000 "clearline"]
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Line[70000 40000 70000 20000 1000 2000 "clearline,rubberend"]
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Line[20000 40000 20000 64200 2500 2000 "clearline"]
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Line[20000 64200 24200 68400 2500 2000 "clearline"]
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)
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Layer(3 "GND")
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(
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@ -1098,6 +1103,8 @@ NetList()
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(
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Connect("D1-2")
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Connect("D2-2")
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Connect("POWER_IN-2")
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Connect("POWER_OUT-2")
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)
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Net("GND_uC" "(unknown)")
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(
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@ -1188,6 +1195,8 @@ NetList()
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Net("VCC_HIGH" "(unknown)")
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(
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Connect("CONF-1")
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Connect("POWER_IN-1")
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Connect("POWER_OUT-1")
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Connect("R2-1")
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Connect("uC-12")
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)
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